(1) Field of the Invention
This invention relates generally to a novel two-transistor (2T) based NVM cell array that is most suitable for traditional Programmable Logic Device (PLD), Programmable Array Logic (PAL) and any matching and comparing function applications.
(2) Description of the Prior Art
In order to implement the above said functions in prior art, each cell uses two 1T NVM transistors connected in parallel with two complementary separate wordlines (WLs) and one common ground as an unit cell to configure it into a NOR-array.
The traditional Programmable Logic Device (PLD) array comprises of a plurality rows and columns. The unit cell is made of two 1T MOS or Bipolar transistors. The MOS PLD prevails on the market place due to its lower power consumption and higher cell scalability over the bipolar counterpart.
FIG. 1a, prior art, 100, shows an exemplary part of a CMOS PLD ROM-based NOR-array with implemented ROM code that comprises of (n+1)-paired rows of A0-An and (m+1) columns of BL0-BLm of prior art with (n+1) paired logic inputs such as the first pair of A0 and A0b to the last pair of An and Anb. As it is well known in the art, the logic of each column of the array is defined as one product term of (n+1) logic inputs for the PLD logic. For example, BL0 logic is defined as one of the product term as the following A0bxA1bx----xAnb,-------, A0xA1x---An. The m+1 columns of bitlines means it provides m+1 product terms.
The basic unit cell is marked within a circle in FIG. 1a and is one paired 1T transistors such as mun0 and mdn0. The two drain nodes of each pair transistors are connected to one common BLm running in Y-axis as a NOR-array. The two separate gates of one paired transistor are connected to two separate wordlines running in X-axis and are connected to one pair of logic inputs such as An and Anb. There are total 2n+2 transistors are connected to one BL when there are (n+1)-paired logic inputs connected to (n+1) paired gates.
The n input logic has one n-value vector to be matched for each product term for each BL. One bit of input logic is defined as A0=VSS and A0b=VDD or A0=VDD and A0B=VSS. Only one transistor out of one-paired transistors of munm and mdnm is non-conducting in read operation when the predetermined pattern is being matched. There are totally 2n+1 combinations of logics of n+1 logic inputs. Any logic of any BL of any one product term to be logic high only happens when all n-paired cells' patterns are matched of that selected BL. Just one cell's paired pattern does not latch the input complementary pattern, the selected BL logic would be low. The is also called as the Certain Check Engine that requires 100% matching bits.
Since this array is actually a 1T NOR array, the matching speed is fast. The disadvantage of the ROM-based PLD is that it cannot provide an in-circuit real time programmability. The mask change has to be done in wafer foundry.
FIG. 1b prior art, 110, shows a part of a CMOS PLD Flash-based NOR-array with programmable memory that comprises of (n+1)-paired rows of A0-An and (m+1) columns of BL0-BLm of prior art with (n+1) paired logic inputs such as the first pair of A0 and A0b to the last pair of An and Anb. As it was well known in the art, the logic of each column of the array is defined as one product term of (n+1) logic inputs for the PLD logic. For example, BL0 logic is defined as one of the product term as the following A0bxA1bx----xAnb, -------, A0xA1x---An. The m+1 columns of bitlines provide m+1 product terms.
The basic unit cell is marked within a circle in FIG. 1b and is one paired 1T transistors such as munm and mdnm. The two drain nodes of each pair transistors are connected to one common BLm running in Y-axis as a NOR-array. The two separate gates of one paired transistor are connected to two separate wordlines running in X-axis and are connected to one pair of logic inputs such as An and Anb. There are total 2n+2 transistors are connected to one BL when there are (n+1)-paired logic inputs connected to (n+1) paired gates.
The n input logic has one n-value vector to be matched for each product term for each BL. One bit of input logic is defined as A0=VSS and A0b=VDD or A0=VDD and A0B=VSS. Only one transistor out of one-paired transistors of munm and mdnm is conducting in read operation when the predetermined pattern is being matched. There are totally 2n+1 combinations of logics of n+1 logic inputs. Any logic of any BL of any one product term to be logic high only happens when all n-paired cells' patterns are matched of that selected BL. Similarly like ROM PLD array, just one cell's paired pattern does not latch the input complementary pattern, the selected BL logic would be low. The is also called as the Certain Check Engine that requires 100% matching bits.
FIG. 1c prior art shows the two Vts of 1T NVM cell used in the NOR-array of either ROM-based PLD or Flash-based PLD of two prior art in FIG. 1a and FIG. 1b. The Vt0 is the lower Vt state which is defined as the conduction state, while the Vt1 is the high Vt one which is defined as non-conducting state. In this NOR-array, both Vt0 and Vt1 definition have to be set to be positive value for the accurate PLD logic implementation. Any one of negative value of Vt0 or Vt1 would result in the BL leakage, thus malfunction of PLD operation.
The gate voltage levels applied to any paired inputs such as A0 and A0b are complementary such as VSS and VDD. The gate that coupled to VDD voltage has to be set higher than Vt0 but below Vt1 with a good margin to ensure the selected cell of Vt0 is biased in a conducting state for accurate PLD operation. Both Vt0 and Vt1 are not the fixed values but have a Vt distribution in reality. The narrower Vt distribution of Vt0 is the better performance and speed for the lower VDD operation. The width of Vt1 distribution is a “don't-care” as long as the gap between the maximum value of Vt0 and the minimum value of Vt1 is wide enough for clean reading. Another disadvantage of this prior 1T PLD NOR-array is the encountering of the over-erase issue that would increase the hassle of erase time and the design challenge. As a consequence, an over-erase-concern free PLD, Programmable Array Logic (PAL) or matching solution without a sacrifice in read speed and scalability are highly required in many market places.